Entry-Level Verification Engineer: Verilog, UVM, SV
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MAXVY Technologies Pvt Ltd
New South Wales
A semiconductor manufacturing company is seeking an entry-level candidate for a role involving design and verification tasks. The ideal candidate should have experience with Verilog, SystemVerilog, and UVM. Responsibilities include designing test plans and developing test cases in UVM/SV and C. Knowledge of APB/AXI/AHB protocols and familiarity with MIPI is preferred. This full-time position... |
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a day ago
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